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Chris Allsup
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Webinars
STMicroelectronics and Synopsys Present: How iCube Technology in TetraMAX II is Breaking the ATPG Sound Barrier, October 27, 2016 STMicroelectronics’ Experience: Synopsys Logic BIST for Automotive and Safety-Critical Designs, July 30, 2015 Advantest and Synopsys: Taking Test Cost Reduction to the Next Level, April 30, 2015 Interviews Experts Roundtable: Design-For-Test, Systems Design Engineering Synopsys addresses yield, memory test, and small delay defects, Test & Measurement World Synopsys develops new ATPG technology, EE Times White papers The Path to (Virtually) Zero Defective Parts Per Million ISO 26262-Certified Solution for Testing of Safety-Critical Automotive ICs DFTMAX Compression shared I/O More effective Test: Slack-Based Transition Delay Test Automation of 3D Integrated Systems |
Selected Articles
Allsup C., An ISO 26262 approach to meeting the cost, quality, reliability, and integration needs of automotive ICs, Tech Design Forum, January 16, 2017 Allsup C., Faster and Fewer Patterns with Breakthrough ATPG to the Rescue EE Times, August 10, 2016 Allsup C., Armstrong D., Cron A., Reducing IC test costs through multisite and concurrent testing, Test Design Forum, November 6, 2015 Allsup C., Test trends: Commercial scan compression tools, The EDN Network, Test-and-measurement Design Center, July 17, 2013 Allsup C., Chung K., DFT strategy for ARM processor-based designs, EDN Network, January 22, 2013 Allsup C., 20nm test demands new design-for-test and diagnostic strategies Tech Design Forum, November 5, 2012 Allsup C., Frank S., Use Advances in Synthesis Technology to Cut Implementation Time, Chip Design Magazine, February 21, 2012 Allsup C., Chen C-A, Chen Y-W, Cron A., The fast track to 3D-IC testing, EE Times, January 16, 2012 Allsup C., Enabling early RTL exploration, Electronics Magazine, December 18, 2011 Allsup C., Is built-in logic redundancy ready for prime time?, 11th International Symposium on Quality Electronic Design (ISQED), March 22, 2010 Allsup C., Dodd C., Using compression to meet pin-limited test requirements, EE Times, January 21, 2010 Allsup C., Kapur R., Predictive solutions for test-The next DFT paradigm?, IEEE International Test Conference, November 2009 Allsup C., Appello D., Mattiuzzo R., Small Delay Defect Testing, Test & Measurement World, June 1, 2009 (download pdf) Allsup C., The Economics of Defect-Based Testing, IEEE International Workshop on Defect & Data-Driven Testing, October 30, 2008 ( download pdf) Allsup C., Lloyd B., Playing it cool, EDN Network, October 1, 2008 Allsup C., Early relief for 45-nm routing congestion, EE Times, April 7, 2008 Allsup C., Design for Low-Power Manufacturing Test, EE Times, March, 18, 2008 Allsup C., Perform Low Power Manufacturing Test, EE Times Asia (download pdf: part 1: January 16, 2008, part 2: February 1, 2008) Allsup C., The Benefits -- And Hazards -- Of Scan Compression, Electronic Design, August 2, 2007 Allsup C., Measuring Scan Compression Performance, EDA Design Line, May 27, 2007 (download pdf) Allsup C., Optimizing compression in scan-based ATPG DFT implementations, The EDN Network, Test-and-measurement Design Center, March 1, 2007 Allsup C., How Design Automation Is Reshaping the Foundry-Client Dynamic, Test and Measurement World, February 2007 ( download pdf) Allsup C., The Economics of Implementing Scan Compression to Reduce Test Data Volume and Test Application Time, IEEE International Test Conference, October 2006 Allsup C., Kapur R., DFT rule checkers glue design together, EE Times Asia, October 16, 2006 ( download pdf) Allsup C., Limits of test time reduction, EDN Network, June 1, 2006 Allsup C., How much test compression is enough? EE Times, Test and Measurement, February 20, 2006 |